1. Field of the Invention
The present invention relates to semiconductor memories and to static memory cells. More particularly, the present invention relates to a static random access memory (SRAM) cell which assumes a known state on power-up.
2. The Prior Art
Static memory devices such as SRAM cells are known to exhibit random initial logic states on power-up of the integrated circuit which contains them. There can be a problem in some logic arrays if a random initial memory state on power-up causes devices controlled by the memory cell in the array (e.g. programmable connection or switching elements such as a MOS transistor pass gate or switch) to become shorted together. Such short circuits may cause the devices controlled by the memory cells to become un-programmable or even damaged. This is a noticeable problem for large arrays. It is therefore desirable to control the initial memory state of the memory cells on power-up.
There have been prior art attempts to solve this problem and to provide a memory cell which assumes a known initial state on power-up. For example, in U.S. Pat. No. 4,821,233, two P-Channel MOS transistors in each memory cell are differently doped to exhibit different threshold voltages. At power-up, as the power supply voltage level rises from 0 volts to the supply voltage level, the one of the two P-channel MOS transistors requiring the lowest voltage differences between the gate and source will turn on first. This P-channel MOS transistor will in turn apply this increasing level to the gate of the other P-channel MOS transistor, thus preventing the other P-channel MOS transistor from turning on during power-up.
While this solution allows controlling the states of the memory cells during power-up, it requires separate masks for the doping of the two P-channel MOS transistors, thereby prohibiting the use of standard CMOS processes to manufacture integrated circuits containing such devices. This scheme has an additional complication which results from mismatching the P-Channel MOS transistors, making one of them harder to turn "off" during normal operation. This is undesirable.
The prior art has suggested changing the channel length of one of the P-Channel MOS transistors to control its threshold voltage and thus avoids the requirement of using non-standard process steps. But the differences in threshold voltages obtained by this method are acknowledged to be small and less reliable than differential doping. The threshold voltage differential can also be non-uniform because of process variations.
Whichever of these solutions is applied, the prior art power-up state cannot be changed since it is mask-dependent or dependent on the altered device physical parameter like channel length.
It is therefore an object of the invention to provide a memory cell which assumes a known state upon power up which avoids the shortcomings of the prior art.
It is a further object of the present invention to provide a memory cell which assumes a known state upon power up wherein the state on power up may be selected by a user.
Yet another object of the invention is to provide a memory cell which assumes a known state upon power up which may be fabricated using standard CMOS processes.